Maintaining signal integrity is a challenge as data rates increase and system designs get increasingly complicated with additional channels side by side. Signals travel through various interconnects inside a system to reach their destination so any electrical degradation induced between the transmitter, connectors, cabling, and printed circuit board (PCB) traces, and the receiver will affect the timing and quality of the signal.
Waveform distortions can be caused by impedance mismatches like stubs and vias, frequency dependent attenuation, and electromagnetic coupling between signal traces (i.e., crosstalk). A high speed signal moving through a channel is also subjected to high frequency impairments such as reflections, dielectric loss, and loss due to the skin effect. These impairments degrade the quality of the signal making it problematic for a receiver to interpret it correctly.
Copper backplanes do not provide adequate bandwidth to support these higher signaling rates, so to improve the quality of a link, signal conditioning devices such as equalizers have been employed.
Equalizers are devices that compensate high frequency impairments induced by a channel between a transmitter and a receiver. Equalization is a signal conditioning technique in which a waveform is manipulated either at the transmitter, at the receiver, or by a signal conditioner somewhere within a link in order to compensate for the distortions.
Transmit equalization pre-distorts a transmitted signal by amplifying the high frequency content of the signal to compensate for the expected amount of loss through the channel. The emphasized portion of the signal is attenuated by the channel resulting in an open eye, which allows the signal to be easily interpreted by the receiver.
Receive equalization compensates a signal after it travels through a channel by restoring high frequency content that was lost due to channel attenuation. One receive equalization technique may be performed by a continuous time linear equalizer (CTLE), sometimes also referred to as a gain peaking amplifier (GPA). Multi stage CTLEs are the least expensive and lowest power option for receive equalization; moreover, CTLEs do not need reference clocks. Equalization circuitry is typically implemented in application specific integrated circuits (ASICs), serializer/deserializer (SerDes) devices and similar circuits, and is typically installed on PCBs in repeaters, drivers, switches, routers, etc.
Reference is now made to FIG. 1 depicting an example application where equalization, and in particular a CTLE, can be used. A first line card 100 and a second line card 102 are coupled to a backplane 104. The first line card 100 includes an ASIC 112 and the second line card includes an ASIC 110. The ASIC 110 on line card 102 includes a transmitter for sending signals and the ASIC 112 on line card 100 includes a receiver having a CTLE. The line card 102 transmits signals to the line card 100 over copper traces on the backplane 104 through connectors 108 and 106. More specifically, the ASIC 110 on line card 102 transmits the signals over the backplane 104 to the receiver at the ASIC 112 on line card 100.
The signaling scheme used is typically one where power is spread over a frequency range. In some wireline applications (e.g., a router, a switch), modulation of digital data is typically accomplished using Non-Return to Zero (NRZ) pulse-amplitude modulation with either 2 (PAM2) or 4 (PAM4) levels. In either PAM2 or PAM4 modulation, the signal power is spread across a large frequency spectrum (from near zero Hertz to 1/Ts or higher, where Ts is the transmitted bit or symbol time duration, e.g., approximately 30-200 picoseconds).
Reference is now made to FIG. 2 depicting a schematic and corresponding block diagram of a prior art continuous time linear equalizer (CTLE) 201, several of which may be cascaded together to form a multi-stage CTLE. The prior art CTLE 201 comprises a source degenerated, transadmittance amplifier (voltage-to-current (V-I) amplifier 200) coupled to a dual gm, transimpedance amplifier (TIA) (current-to-voltage amplifier 202). A conventional current mode logic (CML) boosting stage is configured as the V-I amplifier 200 having a differential input voltage V; applied to the gates of NMOS transistors 205 and 207. A voltage (vcm) representative of the desired or target common-mode voltage at the output of the TIA amplifier stage 202 is generated by a separate reference or bias generator circuit (not shown), the details of which are not required for the present disclosure. The actual output common-mode voltage (vsns) of the TIA stage 202 is sensed at the common node between resistors Rcp and Rcm. Both vcm and vsns are applied to an operational transconductance amplifier (OTA) 206 which is coupled to the gates of PMOS transistors 203 and 204 forming a feedback control loop for regulating the output common-mode voltage of the TIA amplifier stage 202. Alternatively stated, voltage vcm is the reference voltage whereas vsns is the voltage feedback to the control loop. The OTA 206 compares vsns to vcm and adjusts the DC voltage applied to the gate of PMOS transistors 203 and 204 in order to make vsns approach vcm.
Use of the V-I amplifier 200 results in a zero in the simplified differential voltage-to-current transfer function G(s) at a frequency fz1 (shown in FIG. 3) based on the values selected for resistor Rd and capacitor Cd which are coupled in parallel between the sources of NMOS transistors 205 and 207 and the drains of NMOS transistors 209 and 211. Transistors 209 and 211 form a current mirror along with transistor(s) located in bias generator 213. The current (iref) applied to the bias generator 213 is used to generate the gate (bias) voltages applied to transistors 209 and 211. The reference current (iref) is much smaller than the mirrored circuit currents (i11 and i9) yet the current density in the reference transistor(s), and in transistors 209 and 211, is equal. The details of the bias generator 213 are not necessary for the understanding of the present disclosure.
The simplified differential voltage-to-current transfer function G(s) of the V-I amplifier 200 can be expressed from the differential half-circuit representation as:
      G    ⁡          (      s      )        =                    io        ⁡                  (          s          )                            Vi        ⁡                  (          s          )                      =                            gm          nmos                ⁡                  (                      1            +                          s              ⁢                                                          ⁢              C              ⁢                                                          ⁢              d              ⁢                                                          ⁢              R              ⁢                                                          ⁢              d                                )                                      (                      1            +                                          gm                nmos                            ⁢                                                R                  ⁢                                                                          ⁢                  d                                2                                              )                +                  s          ⁡                      (                                          R                ⁢                                                                  ⁢                d                ⁢                                                                  ⁢                C                ⁢                                                                  ⁢                d                            +                                                                    R                    ⁢                                                                                  ⁢                    d                                    2                                ⁢                C                ⁢                                                                  ⁢                g                ⁢                                                                  ⁢                s                                      )                              where gmnmos is the transconductance of transistors 205 and 207 and Cgs is the gate-source capacitance of transistors 205 and 207. The half-circuit derivation is made possible by the symmetry of the circuit. The half-circuit equivalent quantities for Rd and Cd shown in FIG. 2 as connected between both excitation polarities (i.e., differentially connected) are 2*Cd and Rd/2, respectively.
PMOS transistors 203 and 204 in the V-I amplifier 200 are high impedance current mirrors that provide bias currents i3 and i4, which are substantially equal to currents i9 and i11 provided by NMOS transistors 209 and 211. NMOS transistors 205 and 207 steer the current generated by the current mirror NMOS transistors 209 and 211 between nodes nodeintp and nodeintm as a function of the applied input signal Vi. Nominally, with Vin=0V, the differential current between 205 and 207 is zero and equals that between transistors 203 and 204 (where i3−i4=0). In this case, no differential current flows into the TIA stage 202. In contrast, with a non-zero input signal (i.e., Vin≠0), the differential current from 205 and 207 will not equal that provided by PMOS transistors 203 and 204 (i.e., i5−i7≠0). The difference in current (iin) is provided to the TIA amplifier stage 202. The TIA amplifier stage 202 converts the input current iin from the V-I amplifier 200 to an output voltage Vout via transimpedance Rt. The transimpedance is formed by the feedback resistor Rf (Rfp and Rfm) and transistors 208, 212 and 210, 214. The simplified transimpedance (Rt) derived from the differential half-circuit of the TIA stage 202 is:
            V      ⁢                          ⁢      o      ⁢                          ⁢      u      ⁢                          ⁢      t              I      ⁢                          ⁢      i      ⁢                          ⁢      n        =            R      t        =                  1        -                              (                                          g                ⁢                                                                  ⁢                                  m                                      n                    ⁢                                                                                  ⁢                    m                    ⁢                                                                                  ⁢                    o                    ⁢                                                                                  ⁢                    s                                                              +                              g                ⁢                                                                  ⁢                                  m                                      p                    ⁢                                                                                  ⁢                    m                    ⁢                                                                                  ⁢                    o                    ⁢                                                                                  ⁢                    s                                                                        )                    ⁢                      R            f                                                (                                    g              ⁢                                                          ⁢                              m                                  n                  ⁢                                                                          ⁢                  m                  ⁢                                                                          ⁢                  o                  ⁢                                                                          ⁢                  s                                                      +                          g              ⁢                                                          ⁢                              m                                  p                  ⁢                                                                          ⁢                  m                  ⁢                                                                          ⁢                  o                  ⁢                                                                          ⁢                  s                                                              )                +                  (                                    g              ⁢                                                          ⁢              d              ⁢                                                          ⁢                              s                                  n                  ⁢                                                                          ⁢                  m                  ⁢                                                                          ⁢                  o                  ⁢                                                                          ⁢                  s                                                      +                          g              ⁢                                                          ⁢              d              ⁢                                                          ⁢                              s                                  p                  ⁢                                                                          ⁢                  m                  ⁢                                                                          ⁢                  o                  ⁢                                                                          ⁢                  s                                                              )                    where Rf=Rfp=Rfm, gmnmos is the transconductance of the NMOS transistors 212 and 214 and gmpmos is the transconductance of PMOS transistor 208 or 210. The finite output conductance of transistors 208 and 210 is represented by the terms gdspmos, while that of transistors 212 and 214 is gdsnmos.
The TIA amplifier 202 has a low output impedance (Rout) by leveraging the transconductance (gm) of both the PMOS transistors 208, 210 and the NMOS transistors 212, 214. The differential output resistance is given by:
      R    ⁢                  ⁢    o    ⁢                  ⁢    u    ⁢                  ⁢          t      diff        =      2          (                        g          ⁢                                          ⁢                      m            nmos                          +                  g          ⁢                                          ⁢                      m            pmos                              )      where gmnmos is the transconductance of transistors 212, 214, and gmpmos is the transconductance of transistors 208, 210.
Reference is now made to FIG. 3 depicting a Bode diagram of the transfer function for the prior art CTLE 201 shown in FIG. 2. The CTLE 201 depicted in FIG. 2 has a single gain path with a zero in the transfer function at frequency fz1 (set by resistor Rd and capacitor Cd) that provides increasing gain at frequencies higher than fz1. To increase the amount of compensation, many CTLEs 201 can be cascaded as depicted in FIG. 4. This increases the power consumption and amount of integrated circuit die area consumed by the CTLE. Furthermore, low frequency attenuation by the CTLE stages further necessitates the inclusion of DC gain recovery stages interposed between CTLE stages to ensure adequate overall DC gain.
Therefore, there is a need for a CTLE with higher gain peaking at substantially the same power as a traditional boosting stage so that fewer stages (thus less power and silicon area) are required for adequate compensation.